Register for the Event

In an age where object oriented programming skills has become the order of the day, Verillectual at Quark 2013 provides a unique opportunity for electronics enthusiasts to exhibit their Alternative Programming talent in System based Analog and Digital Design, by circumventing the traditional component-on-board approach to System design, substituting it by the extremely versatile and algorithm driven programming of HDLs (Hardware Description Languages).

However, simply good programming skills does not qualify a good Electronics Engineer, which is why Verillectual requires participants to be able to sufficiently design and simulate the system model that they have generated using abstracted electronic component design on EDA tools.

You can download the Problem Set for Round 1 here.



Event Specification:

Round 1 (Online elimination)

This round is an off-campus online elimination round. For this round, each team is expected to submit a working code and a test bench or instruction for simulation to test it. Both have to be mailed in .doc or .pdf format on or before the deadline. Simulation can be done in Modelsim® or Xilinx with help of a test bench. The solutions are to be submitted online to [email protected]

Round 2 (On-Campus round)

It’s an on-campus round which would test  the aptitude of the participants for HDL-based system design and implementation skills of the selected teams. In this round, participants are given a few real-life problems in the Anchor design of a digital system or parts of a digital system and are expected to come up with an implementable model for their system that can be simulated. The details of this round will be communicated to the selected participants in due course of time.
Round 3 (On-campus Final Round)

The top teams from the 2nd round will be selected to participate in the final round. The participants will be given one real life problem and are expected to put together the full implementable model for their system. The complete details of the final round will be communicated in due course of time.


1. the First Round, each team is expected to submit a working code and a test bench or instruction for simulation to test it. Both have to be mailed in .doc/.pdf format before the deadline.
2. Solutions for this round can be submitted for a maximum of three times. But only the latest solution will be evaluated.
3. Any assumptions made to solve the problem must be clearly mentioned along with the solution. This is valid for both the rounds of the event.
4. The Code must be in either Verilog (IEEE 1364-2001 standard). Note that only the above mentioned standards of Verilog shall be accepted.
In the second round, students will be allowed access to any reference material as well as any book on Verilog of their choice. The selected teams for the second round will be expected to bring any such material to Quark before appearing for the second round. Exchange of any kind of material, during this round, between the participating teams is not allowed.
5. Usage of internet during the final round of the event is NOT allowed.


    All students with a valid identity card of their respective educational institutes are eligible to participate in the event.
    Participants are expected to have basic knowledge of either Verilog/VHDL.

Certification Policy:

    Certificate of Merit will be given to the first three winning teams.
    Certificates of Participation will be given to all the teams who qualify and report for the final round.

Team Specifications:

Minimum : 1 members
Maximum : 3 members

Judging Criteria

  1.The judging criteria for the first round would mainly be the efficiency of the logic algorithm and the HDL code. Contestants shall be evaluated relative to each other (for e.g. in case of a tie, relative to the most efficient description of the same code)

  2. In the second and third round, emphasis is laid on detailed knowledge of design and implementation parameters, since this round would inevitably involve design of a real-life application. Participants will be required to explain their algorithms to the judges, if required.

  3. Compilation of the code without any errors and warning will also carry weightage in both the rounds.

  4. Additional Rules for the second round, if any, will be communicated to the participants well in advance.

  5. If no team is able to successfully complete the final round, the team that has concluded the largest portion of their assigned system will be adjudged the winners.

  6. Judges' decision shall be treated as final and binding on all. Judges reserve the right to disqualify any team found indulging in misbehavior /cheating.



Digital Design – Morris Mano

Verilog HDL – Samir Palnitkar




If you have any query, please send an e-mail to [email protected] or get in touch with any one of us:

Kshitij Jain                                                            Sumedh Kaulgud
+917709790425                                                  +919604438183
[email protected]                                       [email protected]