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VLSI Design

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PRIZES WORTH Rs. 15,000 TO BE WON!!

Introduction

This event provides electronics enthusiasts a hands-on experience in embedded logic. The goal of the contest is to help students cultivate design interests in VLSI, to improve their design techniques and to put their creativity and innovation into practice as they try their hand at the technology which is the talk of the industry today. So, for all those passionate about digital electronics, we bring you an event that challenges your coding abilities to the hilt.

Event Specifications

The event has 2 rounds:

Round 1 (Online elimination)

  • The problem statement can be downloaded from the links provided below.
  • The teams need to submit a working code in either VHDL or Verilog and a Testbench along with it to test the code.
  • Mail the entries to [email protected]

Problem statement

Introduction to Differential Manchester line coding

 

Round 2 (On-Campus Final round)

  • This round will test the aptitude, of the selected teams, in system designing.
  • The teams will be asked to design a real-life control system. They need to be creative and innovative and come up with a solution that is most realistic and efficient.
  • The participants may also use tools like EDK, System Generator and Chipscope Pro wherever required.

Rules

  • Each team can comprise of a maximum of three members.
  • Each team is required to submit a properly working code and a Testbench to test it. Both have to be mailed in txt/doc/pdf format before the deadline.
  • Any assumptions made to solve the problem must be clearly mentioned while submitting the solution.
  • The Code/Testbench can be in either Verilog (IEEE 1364-2001 standard) /VHDL (IEEE standard 1164). The above mentioned standards of Verilog/VHDL are preferred.
  • In the second round, students will be allowed to use any reference material as well as any book on VHDL/Verilog of their choice.
  • The selected candidates for the second round will be expected to bring any such material to Quark before appearing for the second round. Net facility can be availed by the participants during the event.

Judging Criteria

  • The selection for the first round will be done depending on the accuracy of the team’s solution.
  • In the second round, more emphasis will be laid on innovation and efficiency of the design.
  • Priority will be given to the strategies employed by the participants to accomplish the given goal.
  • Judges' decision shall be treated as final and binding on all. Judges reserve the right to disqualify any team indulging in misbehaviour.

Eligibility

  • All students with a valid identity card of their respective educational institutes are eligible to participate in the event.
  • Participants are expected to have basic knowledge of either Verilog/VHDL.
  • Preferably, the participants are advised to have knowledge about EDK, Chipscope Pro and System Generator that comes along with Xilinx ISE suite. Even otherwise, complete knowledge about the software will be provided during the Pre-Quark and Quark workshop.
  • Also, no prior knowledge of FPGA’s is essential. All the participants will be trained to use it, during Quark, one day in advance.

Certification Policy

  • Certificate of Excellence will be awarded to the emerging winners.
  • Certificates of Participation will be awarded to all the teams who qualify for the final round.

Event Managers

If you have any queries, please send an email to [email protected], or get in touch with any one of us:

Girish Assudani
[email protected]
+91 9923811270

Vaibhav Sinha
[email protected]
+91 9673976801