Digital Inciso

                                                                                                           Winners will reap prizes worth 15000 INR!!Hurry Up Now!!!

Always been fascinated by how stuff works? Love getting to the core of things to figure 'em out? Itching to use your theoretical knowledge to real life applications? Well, then this Quark, we bring to you Digital Inciso, where the brightest in the country engage in a skirmish of codes. We'll keep your heads scratching as you test your mettle in digital design and architecture using Verilog. Are you ready to take on the

Problem Statement for the online round is up! Check it out NOW!

Results for the first round of Digital Inciso are out. Click here. Selected participants must check their emails for details of Round 2.

Details

Event Specification:

Round 1 (Online elimination):

This round is an off-campus online elimination round. For this round, each team is expected to submit a working code and a test bench or instruction for simulation to test it. Both have to be mailed in .doc or .pdf format on or before the deadline. Simulation can be done in Modelsim® or in Xilinx® with help of a test bench. The solutions are to be submitted online to [email protected]
Check out the problem statement here.

Round 2(On-Campus Final round):

This round is the second and final round. Its an on-campus round which would test  the aptitude of the participants for HDL-based system design and implementation skills of the selected teams. In this round, participants are given a real-life problem in the Anchor design of a digital system or parts of a digital system and are expected to come up with an implementable model for their system that can be simulated. The details of this round will be communicated to the selected participants in due course of time.

Rules

Rules:

• For the First Round, each team is expected to submit a working code and a test bench or instruction for simulation to test it. Both have to be mailed in .doc/.pdf format before the deadline.
• Solutions for this round can be submitted for a maximum of three times. But only the latest solution will be evaluated.
• Any assumptions made to solve the problem must be clearly mentioned along with the solution. This is valid for both the rounds of the event.
• The Code must be in either Verilog (IEEE 1364-2001 standard). Note that only the above mentioned standards of Verilog shall be accepted.
• In the second round, students will be allowed access to any reference material as well as any book on Verilog of their choice. The selected teams for the second round will be expected to bring any such material to Quark before appearing for the second round. Exchange of any kind of material, during this round, between the participating teams is not allowed.
• Usage of internet during the final round of the event is NOT allowed.

Eligibility:

    All students with a valid identity card of their respective educational institutes are eligible to participate in the event.

    Participants are expected to have basic knowledge of Verilog.

Certification Policy:

    Certificate of Merit will be given to the first three winning teams.

    Certificates of Participation will be given to all the teams who qualify and report for the final round.

Team Specifications:

Judging Criteria

Judging Criteria:

• The judging criteria for the first round would mainly be efficiency of the logic algorithm and the HDL code. Contestants shall be evaluated relative to each other (for e.g. in case of a tie, relative to the most efficient description of the same code)
•  In the second round, emphasis is laid on detailed knowledge of design and implementation parameters, since this round would inevitably involve design of a real-life application. Participants will be required to explain their algorithms to the judges, if required. Compilation of the code without any errors and warning will also carry weightage in both the rounds.
•  Additional Rules for the second round, if any, will be communicated to the participants well in advance.
•  If no team is able to successfully complete the final round, the team that has concluded the largest portion of their assigned system will be adjudged the winners.
• Judges' decision shall be treated as final and binding on all. Judges reserve the right to disqualify any team found indulging in misbehavior /cheating.

Resources

http://esd.cs.ucr.edu/labs/tutorial/

http://www.asic-world.com/verilog/veritut.html

http://www.asic-world.com/vhdl/tutorial.html

http://www.play-hookey.com/digital/

http://electrosofts.com/verilog/

http://www.verilogwiki.info/wiki/index.php/Tutorials

http://www.verilogtutorial.info/

Additional Links:

http://www.scribd.com/doc/27815630/10-Parity-Checker-Circuit

http://www.electronics-tutorials.ws/counter/count_3.html

http://www.electronics-tutorials.ws/counter/count_4.html

http://www.allaboutcircuits.com/vol_4/chpt_11/3.html

Contacts

Sai Prasanth
+91 9657294672

Sudhamai
+91 9561957502